From 309d36182ef32a1bc5bff84f39e9e81db0ddb9a6 Mon Sep 17 00:00:00 2001 From: Ekaitz Zarraga Date: Fri, 23 Jul 2021 20:28:36 +0200 Subject: Add baseassembler --- pyscv/baseassembler.py | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 pyscv/baseassembler.py diff --git a/pyscv/baseassembler.py b/pyscv/baseassembler.py new file mode 100644 index 0000000..e65a5bd --- /dev/null +++ b/pyscv/baseassembler.py @@ -0,0 +1,33 @@ +from registers.RV32I import * +from InstructionSets.RV64I import * + + +Regs = RegistersRV32I() + +def x(registerName): + return Regs.getPos(registerName) + +def compileBigEndian(instruction): + hexrepr = hex(instruction.compile().value) + hexval = hexrepr[2:] + if len(hexval) < 8: + hexval = "0" * (8 - len(hexval)) + hexval + + final = "" + for i in range(0,8,2): + final += hexval[i:i+2] + " " + return final.rstrip().upper() + +def compileLittleEndian(instruction): + hexrepr = hex(instruction.compile().value) + hexval = hexrepr[2:] + if len(hexval) < 8: + hexval = "0" * (8 - len(hexval)) + hexval + + final = "" + for i in range(0,8,2): + final += hexval[i:i+2] + " " + final = final.rstrip().upper() + return " ".join(reversed(final.split(" "))) + + -- cgit v1.2.3