From c2a68e27031656257068a5d351519f50c0d5631a Mon Sep 17 00:00:00 2001
From: Ekaitz Zarraga <ekaitz@elenq.tech>
Date: Mon, 24 May 2021 11:14:10 +0200
Subject: Add more instructions to RV32I

---
 pysc-v/InstructionSets/RV32I.py | 128 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 128 insertions(+)

diff --git a/pysc-v/InstructionSets/RV32I.py b/pysc-v/InstructionSets/RV32I.py
index 8950252..7f4a428 100644
--- a/pysc-v/InstructionSets/RV32I.py
+++ b/pysc-v/InstructionSets/RV32I.py
@@ -285,6 +285,53 @@ class andi(I):
     funct3  = 0b111
 
 
+class ShiftImm(I):
+    # NOTE: This is an special type used for shifting operations because they
+    # have 7 bits left after the maximum shift (5bits -> 32 rotations)
+    # they can apply.
+    # In RV64I they can indicate rotation with 1 bit more (64 rotations) so
+    # they use a funct6 instead.
+    funct7 = None
+    funct3 = None
+    opcode = None
+
+    def __init__(self, rd, rs, imm):
+        self.rd  = rd
+        self.rs  = rs
+        self.imm = imm
+
+    def compile(self):
+        return c_uint32(
+            (self.funct7 << 25) +\
+            (self.imm    << 20) +\
+            (self.rs     << 15) +\
+            (self.funct3 << 12) +\
+            (self.rd     <<  7) +\
+            self.opcode
+        )
+
+@RV32I.instruction
+class slli(ShiftImm):
+    name    = "slli"
+    opcode  = 0b0010011
+    funct3  = 0b001
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class srli(ShiftImm):
+    name    = "srli"
+    opcode  = 0b0010011
+    funct3  = 0b101
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class srai(ShiftImm):
+    name    = "srai"
+    opcode  = 0b0010011
+    funct3  = 0b101
+    funct7  = 0b0100000
+
+
 @RV32I.instruction
 class add(R):
     name    = "add"
@@ -296,6 +343,87 @@ class add(R):
         # TODO
         return pc + self.size
 
+@RV32I.instruction
+class sub(R):
+    name    = "sub"
+    opcode  = 0b0110011
+    funct3  = 0b000
+    funct7  = 0b0100000
+
+@RV32I.instruction
+class sll(R):
+    name    = "sll"
+    opcode  = 0b0110011
+    funct3  = 0b001
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class slt(R):
+    name    = "slt"
+    opcode  = 0b0110011
+    funct3  = 0b010
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class sltu(R):
+    name    = "sltu"
+    opcode  = 0b0110011
+    funct3  = 0b011
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class xor(R):
+    name    = "xor"
+    opcode  = 0b0110011
+    funct3  = 0b100
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class srl(R):
+    name    = "srl"
+    opcode  = 0b0110011
+    funct3  = 0b101
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class sra(R):
+    name    = "sra"
+    opcode  = 0b0110011
+    funct3  = 0b101
+    funct7  = 0b0100000
+
+@RV32I.instruction
+class or(R):
+    name    = "or"
+    opcode  = 0b0110011
+    funct3  = 0b110
+    funct7  = 0b0000000
+
+@RV32I.instruction
+class and(R):
+    name    = "and"
+    opcode  = 0b0110011
+    funct3  = 0b111
+    funct7  = 0b0000000
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 @RV32I.pseudoinstruction
 class j(J):
     name    = "j"
-- 
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