From 681036ddc3891904f13c84197cd90e2472cb3e1c Mon Sep 17 00:00:00 2001
From: Ekaitz Zarraga <ekaitz@elenq.tech>
Date: Fri, 23 Jul 2021 20:49:14 +0200
Subject: Change folder name

---
 pyscv/registers/RV32F.py | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 pyscv/registers/RV32F.py

(limited to 'pyscv/registers/RV32F.py')

diff --git a/pyscv/registers/RV32F.py b/pyscv/registers/RV32F.py
new file mode 100644
index 0000000..8e3fd28
--- /dev/null
+++ b/pyscv/registers/RV32F.py
@@ -0,0 +1,45 @@
+from RV32I import RegistersRV32I
+
+class RegistersRV32F(RegistersRV32I):
+
+    def __init__(self):
+        self.names = {}
+        self.data = []
+
+        self.setter = []
+        self.getter = []
+
+        self.lastChange = None
+
+        self.addRegister(("f0","ft0"))
+        self.addRegister(("f1","ft1"))
+        self.addRegister(("f2","ft2"))
+        self.addRegister(("f3","ft3"))
+        self.addRegister(("f4","ft4"))
+        self.addRegister(("f5","ft5"))
+        self.addRegister(("f6","ft6"))
+        self.addRegister(("f7","ft7"))
+        self.addRegister(("f8","fs0"))
+        self.addRegister(("f9","fs1"))
+        self.addRegister(("f10","a0"))
+        self.addRegister(("f11","a1"))
+        self.addRegister(("f12","a2"))
+        self.addRegister(("f13","a3"))
+        self.addRegister(("f14","a4"))
+        self.addRegister(("f15","a5"))
+        self.addRegister(("f16","a6"))
+        self.addRegister(("f17","a7"))
+        self.addRegister(("f18","fs2"))
+        self.addRegister(("f19","fs3"))
+        self.addRegister(("f20","fs4"))
+        self.addRegister(("f21","fs5"))
+        self.addRegister(("f22","fs6"))
+        self.addRegister(("f23","fs7"))
+        self.addRegister(("f24","fs8"))
+        self.addRegister(("f25","fs9"))
+        self.addRegister(("f26","fs10"))
+        self.addRegister(("f27","fs11"))
+        self.addRegister(("f28","ft8"))
+        self.addRegister(("f29","ft9"))
+        self.addRegister(("f30","ft10"))
+        self.addRegister(("f31","ft11"))
-- 
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