From bf457baaf3dc5e05dd16eeca2650ebd15ee9a226 Mon Sep 17 00:00:00 2001
From: Ekaitz Zarraga <ekaitz@elenq.tech>
Date: Sat, 23 Jan 2021 21:12:29 +0100
Subject: Add spike for RISC-V development
---
riscv.scm | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 riscv.scm
diff --git a/riscv.scm b/riscv.scm
new file mode 100644
index 0000000..176295a
--- /dev/null
+++ b/riscv.scm
@@ -0,0 +1,29 @@
+(define-module (riscv)
+ #:use-module (guix packages)
+ #:use-module (guix git-download)
+ #:use-module ((guix licenses) #:prefix license:)
+ #:use-module (guix build-system gnu)
+ #:use-module (gnu packages bootloaders) ; For spike
+ )
+
+
+(define-public spike
+ (package
+ (name "spike")
+ (version "1.0.0")
+ (source (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/riscv/riscv-isa-sim.git")
+ (commit (string-append "v" version))))
+ (file-name (git-file-name name version))
+ (sha256 (base32 "1hcl01nj96s3rkz4mrq747s5lkw81lgdjdimb8b1b9h8qnida7ww"))))
+
+ (propagated-inputs
+ `(("dtc" ,dtc)))
+ (build-system gnu-build-system)
+ (home-page "https://github.com/riscv/riscv-isa-sim")
+ (description "Spike, the RISC-V ISA Simulator, implements a functional
+model of one or more RISC-V harts.")
+ (synopsis "RISC-V ISA Simulator")
+ (license license:gpl3+)))
--
cgit v1.2.3