diff options
| author | Ekaitz Zarraga <ekaitz@elenq.tech> | 2024-09-22 21:51:57 +0200 |
|---|---|---|
| committer | Ekaitz Zarraga <ekaitz@elenq.tech> | 2024-09-22 21:51:57 +0200 |
| commit | bf3289a986f35a7e297caccc442dda0e423f5737 (patch) | |
| tree | c55060bade40a31305bb9d2a631b2091a37f1c37 | |
| parent | 4371a6e83c5c3e0401d2c5e038271b061beff882 (diff) | |
bibliography: add url for open access when missing
| -rw-r--r-- | bibliography.bib | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/bibliography.bib b/bibliography.bib index ba38815..f368801 100644 --- a/bibliography.bib +++ b/bibliography.bib @@ -125,7 +125,8 @@ title = {The Problem with Threads}, volume = {39}, journal = {Computer}, - doi = {10.1109/MC.2006.180} + doi = {10.1109/MC.2006.180}, + url = {https://www2.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-1.pdf} } @inproceedings{ fork:Baumann, @@ -134,7 +135,8 @@ Roscoe, Timothy}, booktitle={Proceedings of the Workshop on Hot Topics in Operating Systems}, pages={14--22}, - year={2019} + year={2019}, + url={https://www.microsoft.com/en-us/research/uploads/prod/2019/04/fork-hotos19.pdf} } @article{ MythsPL:Shaw, @@ -163,7 +165,8 @@ pages={9-19}, keywords={Hardware;Computer architecture;Virtual machining;Microarchitecture;Microprocessors;Software development}, - doi={10.1109/MM.2019.2897677} + doi={10.1109/MM.2019.2897677}, + url={https://ieeexplore.ieee.org/document/8634886} } @@ -246,7 +249,8 @@ pages={136-143}, keywords={Privacy;Conferences;Supply chains;Hardware;Software;Trojan horses;Computer security}, - doi={10.1109/SPW50608.2020.00039} + doi={10.1109/SPW50608.2020.00039}, + url={https://ieeexplore.ieee.org/document/9283874} } % https://www.contrib.andrew.cmu.edu/~somlo/BTCP/ @inbook{EvolutionComputing:Larus, @@ -442,7 +446,7 @@ volume = {51}, number = {4}, issn = {0360-0300}, - url = {https://doi.org/10.1145/3193827}, + url = {https://wrap.warwick.ac.uk/id/eprint/100301/7/WRAP-FPGA-dynamic-partial-reconfiguration-methods-Fahmy-2018.pdf}, doi = {10.1145/3193827}, abstract = {Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have @@ -500,7 +504,7 @@ volume = {37}, number = {6}, issn = {0362-1340}, - url = {https://doi.org/10.1145/571727.571736}, + url = {https://okmij.org/ftp/papers/SXML-paper.pdf}, doi = {10.1145/571727.571736}, journal = {SIGPLAN Not.}, month = {jun}, |