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authorEkaitz Zarraga <ekaitz@elenq.tech>2021-05-24 11:19:41 +0200
committerEkaitz Zarraga <ekaitz@elenq.tech>2021-05-24 11:19:41 +0200
commitdfc17c3ab7ed22e19db7b62f86079cceaa79af12 (patch)
treee90f4eb67ac81ed7f3e07c86e75445d26048f9c8
parentc2a68e27031656257068a5d351519f50c0d5631a (diff)
Add ecall and ebreak
-rw-r--r--pysc-v/InstructionSets/RV32I.py24
1 files changed, 24 insertions, 0 deletions
diff --git a/pysc-v/InstructionSets/RV32I.py b/pysc-v/InstructionSets/RV32I.py
index 7f4a428..5992869 100644
--- a/pysc-v/InstructionSets/RV32I.py
+++ b/pysc-v/InstructionSets/RV32I.py
@@ -406,8 +406,32 @@ class and(R):
funct3 = 0b111
funct7 = 0b0000000
+@RV32I.instruction
+class ecall(I):
+ name = "ecall"
+ opcode = 0b1110011
+ funct3 = 0b000
+
+ def __init__(self):
+ # NOTE: ecall is a I-type instruction but doesn't get any arg and sets
+ # every field to 0
+ self.rd = 0b00000
+ self.rs = 0b00000
+ self.imm = 0b000000000000
+@RV32I.instruction
+class ebreak(I):
+ name = "ebreak"
+ opcode = 0b1110011
+ funct3 = 0b000
+
+ def __init__(self):
+ # NOTE: ebreak is a I-type instruction but doesn't get any arg and pre-
+ # -sets every field to a fixed value
+ self.rd = 0b00000
+ self.rs = 0b00000
+ self.imm = 0b000000000001