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path: root/pysc-v/InstructionSets/RV32I.py
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Diffstat (limited to 'pysc-v/InstructionSets/RV32I.py')
-rw-r--r--pysc-v/InstructionSets/RV32I.py71
1 files changed, 71 insertions, 0 deletions
diff --git a/pysc-v/InstructionSets/RV32I.py b/pysc-v/InstructionSets/RV32I.py
new file mode 100644
index 0000000..967b24d
--- /dev/null
+++ b/pysc-v/InstructionSets/RV32I.py
@@ -0,0 +1,71 @@
+from instructions import Instruction, InstructionSet
+
+RV32I = InstructionSet()
+
+class R(Instruction):
+ funct3 = None
+ funct7 = None
+ opcode = None
+ def __init__(self, rd, rs1, rs2):
+ self.rd = rd
+ self.rs1 = rs1
+ self.rs2 = rs2
+
+ def compile(self):
+ # TODO: ensure sizes and convert register names to number...
+ return c_uint32(
+ (self.funct7 << 25) +\
+ (self.rs2 << 20) +\
+ (self.rs1 << 15) +\
+ (self.funct3 << 12) +\
+ (self.rd << 7) +\
+ self.opcode
+ )
+
+class I(Instruction):
+ funct3 = None
+ opcode = None
+
+ def __init__(self, rd, rs, imm):
+ self.rd = rd
+ self.rs = rs
+ self.imm = imm
+
+ def compile(self):
+ return c_uint32(
+ (self.imm << 20) +\
+ (self.rs << 15) +\
+ (self.funct3 << 12) +\
+ (self.rd << 7) +\
+ self.opcode
+ )
+
+class S(Instruction):
+ pass
+
+class B(Instruction):
+ pass
+
+class U(Instruction):
+ pass
+
+class J(Instruction):
+ pass
+
+
+class add(R):
+ name = "add"
+ opcode = 0b0110011
+ funct3 = 0b000
+ funct7 = 0b0000000
+
+ def execute(self):
+ return pc + self.size
+
+class addi(I):
+ name = "addi"
+ opcode = 0b0010011
+ funct3 = 0b000
+
+ def execute(self):
+ pass