diff options
author | Ekaitz Zarraga <ekaitz@elenq.tech> | 2023-10-31 11:13:35 +0100 |
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committer | Ekaitz Zarraga <ekaitz@elenq.tech> | 2023-10-31 11:13:35 +0100 |
commit | 5861d6e8598543cba97035150124f3f3b6f1e656 (patch) | |
tree | 7b5b3fcc3df33f32c8d22bd50a9df4b38764cb7d /content/bootstrapGcc | |
parent | 80a0d99ac166e54249d1d6a33ec79ae03c7d9c09 (diff) |
bootstrap 08: use shift instead of rot
Diffstat (limited to 'content/bootstrapGcc')
-rw-r--r-- | content/bootstrapGcc/08_tcc_and_mescc.md | 32 |
1 files changed, 19 insertions, 13 deletions
diff --git a/content/bootstrapGcc/08_tcc_and_mescc.md b/content/bootstrapGcc/08_tcc_and_mescc.md index 43666fb..3c18a39 100644 --- a/content/bootstrapGcc/08_tcc_and_mescc.md +++ b/content/bootstrapGcc/08_tcc_and_mescc.md @@ -45,7 +45,7 @@ This is going to be veery long post, so take a ToC to help you out: 7. [Bootstrappable TinyCC's `long double` support was missing](#long-double) 8. [MesCC struct initialization issues](#mescc-struct-init) 9. [MesCC vs TinyCC size problems](#size-problems) - 10. [MesCC add support for signed rotation](#mes-signed-rotation) + 10. [MesCC add support for signed shift operation](#mes-signed-shift) 11. [MesCC switch/case falls-back to default case](#broken-case) 12. [Boostrappable TinyCC problems with GOT](#got) 13. [Bootstrappable TinyCC generates wrong assembly in conditionals](#wrong-conditionals) @@ -433,10 +433,10 @@ wide. You can see this happening in `riscv64-gen.c`, for example, here: EI(0x13, 0, rr, rr, (int)pi << 20 >> 20); // addi RR, RR, lo(up(fc)) ``` -The rotation there is done to clear the upper 20 bits of the pi variable. This -code's behavior might be different from one platform to another. Taking the -example before, of that possible platform that only has 8 bit integers, this -code would send a `0` instead of the lower 12 bits of `pi`. +The bit shifting there is done to clear the upper 20 bits of the pi variable. +This code's behavior might be different from one platform to another. Taking +the example before, of that possible platform that only has 8 bit integers, +this code would send a `0` instead of the lower 12 bits of `pi`. In our case, we had MesCC using the whole register width, 64bits, for temporary values so the lowest `44` bits were left and the next assertion that checked @@ -461,18 +461,18 @@ we all became paranoids about integers and we still think some extra errors will arise from them in the future. Integers are hard. -#### MesCC add support for signed rotation {#mes-signed-rotation} +#### MesCC add support for signed shifting {#mes-signed-shift} Integers were in our minds for long, as described in the previous block, but I didn't talk about signedness in that one. Following one of the crazy errors we had in TinyCC, I somehow realized (I don't -remember how!) that we were missing signed rotation support in MesCC. I think +remember how!) that we were missing signed shifting support in MesCC. I think that I found this while doing some research of the code MesCC was outputting -when I spotted some rotations done using unsigned instructions for signed +when I spotted some bit shifts done using unsigned instructions for signed values and I started digging in MesCC to find out why. I finally realized that -there was no support for that and the rotation operation wasn't selected -depending on the signedness of the value being rotated. +there was no support for that and the shift operation wasn't selected +depending on the signedness of the value being shifted. Let's see this with an example: @@ -487,17 +487,23 @@ a >> 4; b >> 4; ``` -In the example you can see the rotation operation does not work the same way if +In the example you can see the shifting operation does not work the same way if the value is signed or not. If you always use the unsigned version of the `>>` operation, you don't have the results you expected. Signs are also hard. In this case, like in many others, the fix was easier than realizing what was -going wrong. I just added support for the signed rotation operation, not only +going wrong. I just added support for the signed shifting operation, not only for RISC-V but for all architectures, and I added the correct signedness check -to the rotation operation to select the correct instruction. The patch (see +to the shifting operation to select the correct instruction. The patch (see [88f24ea8][signed-rotation] in Mes) is very clean and easy to read, because MesCC's codebase is really well ordered. +> EDIT: Some person in the web noted I called the *bit-shift* operations +> *rotation* operations. I normally use both words interchangeably but it is +> true they don't mean the exact same thing. A shift is when the values are +> lost, and a rotation when they come from the other side of the register. I +> edited the article to use the correct word. + [signed-rotation]: https://github.com/ekaitz-zarraga/mes/commit/88f24ea8661dd279c2a919f8fbd5f601bb2509ae |