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authorEkaitz Zarraga <ekaitz@elenq.tech>2021-07-23 20:49:14 +0200
committerEkaitz Zarraga <ekaitz@elenq.tech>2021-07-23 20:49:14 +0200
commit681036ddc3891904f13c84197cd90e2472cb3e1c (patch)
tree080b9580c14274698d1848e7640cba0cc47a53a6
parent309d36182ef32a1bc5bff84f39e9e81db0ddb9a6 (diff)
Change folder nameHEADmaster
-rw-r--r--pyscv/Frontend/__init__.py (renamed from pysc-v/Frontend/__init__.py)0
-rw-r--r--pyscv/Frontend/lexer.py (renamed from pysc-v/Frontend/lexer.py)37
-rw-r--r--pyscv/Frontend/logger.py (renamed from pysc-v/Frontend/logger.py)0
-rw-r--r--pyscv/Frontend/parser.py (renamed from pysc-v/Frontend/parser.py)0
-rw-r--r--pyscv/Frontend/reader.py (renamed from pysc-v/Frontend/reader.py)2
-rw-r--r--pyscv/InstructionSets/RV32C.py (renamed from pysc-v/InstructionSets/RV32C.py)0
-rw-r--r--pyscv/InstructionSets/RV32D.py (renamed from pysc-v/InstructionSets/RV32D.py)0
-rw-r--r--pyscv/InstructionSets/RV32F.py (renamed from pysc-v/InstructionSets/RV32F.py)0
-rw-r--r--pyscv/InstructionSets/RV32I.py (renamed from pysc-v/InstructionSets/RV32I.py)5
-rw-r--r--pyscv/InstructionSets/RV64I.py (renamed from pysc-v/InstructionSets/RV64I.py)0
-rw-r--r--pyscv/InstructionSets/__init__.py (renamed from pysc-v/InstructionSets/__init__.py)0
-rw-r--r--pyscv/InstructionSets/instructions.py (renamed from pysc-v/InstructionSets/instructions.py)0
-rw-r--r--pyscv/main.py (renamed from pysc-v/main.py)5
-rw-r--r--pyscv/memory.py (renamed from pysc-v/memory.py)0
-rw-r--r--pyscv/registers/RV32F.py (renamed from pysc-v/registers/RV32F.py)0
-rw-r--r--pyscv/registers/RV32I.py (renamed from pysc-v/registers/RV32I.py)0
-rw-r--r--pyscv/registers/__init__.py (renamed from pysc-v/registers/__init__.py)0
17 files changed, 40 insertions, 9 deletions
diff --git a/pysc-v/Frontend/__init__.py b/pyscv/Frontend/__init__.py
index e69de29..e69de29 100644
--- a/pysc-v/Frontend/__init__.py
+++ b/pyscv/Frontend/__init__.py
diff --git a/pysc-v/Frontend/lexer.py b/pyscv/Frontend/lexer.py
index c4a9a7d..f7ca18a 100644
--- a/pysc-v/Frontend/lexer.py
+++ b/pyscv/Frontend/lexer.py
@@ -1,5 +1,5 @@
# TODO Logging is interesting for debugging purposes, decide what to do with it
-from logger import newlogger
+from .logger import newlogger
logger = newlogger(__name__)
#import logging
#logger.setLevel(logging.WARN)
@@ -8,7 +8,7 @@ logger = newlogger(__name__)
######
from enum import Enum
-from reader import Reader
+from .reader import Reader
binChars = set("01")
octChars = set("01234567")
@@ -53,6 +53,10 @@ class Lexer:
self.reader.advance()
return (TokenType.end, None)
+ # Spaces
+ elif self.reader.char.isspace():
+ self.reader.advance()
+
# Argument separator
elif self.reader.char == ",":
self.reader.advance()
@@ -89,16 +93,20 @@ class Lexer:
elif self.reader.char.isdigit() or self.reader.char == "-":
return self.number()
- # Identifiers
- elif self.reader.char.isalpha():
+ # Identifiers or labels
+ elif self.reader.char.isalpha() or self.reader.char == "_":
return self.identifier()
+ # Directive
+ elif self.reader.char == "." and self.reader.peek().isalpha():
+ return self.directive()
+
elif self.reader.char == "":
break # FILE END
else:
- # TODO: Remove this, it's just for testing
- self.reader.advance()
+ raise ValueError("Don't know how to lex")
+
except Exception as e:
# Handle exceptions
# raise StopIteration
@@ -255,11 +263,26 @@ class Lexer:
def identifier(self):
+ logger.info("Found identifier")
+ s = ""
+ while self.reader.char.isalnum() or self.reader.char == "_":
+ s += self.reader.char
+ self.reader.advance()
+
+ if self.reader.char == ":":
+ self.reader.advance()
+ return (TokenType.label, s)
+ else:
+ return (TokenType.identifier, s)
+
+ def directive(self):
+ logger.info("Found directive")
s = ""
+ self.reader.advance() # Discard leading dot
while self.reader.char.isalnum() or self.reader.char == "_":
s += self.reader.char
self.reader.advance()
- return (TokenType.identifier, s)
+ return (TokenType.directive, s)
if __name__ == "__main__":
import sys
diff --git a/pysc-v/Frontend/logger.py b/pyscv/Frontend/logger.py
index a0f76e1..a0f76e1 100644
--- a/pysc-v/Frontend/logger.py
+++ b/pyscv/Frontend/logger.py
diff --git a/pysc-v/Frontend/parser.py b/pyscv/Frontend/parser.py
index b5acfbb..b5acfbb 100644
--- a/pysc-v/Frontend/parser.py
+++ b/pyscv/Frontend/parser.py
diff --git a/pysc-v/Frontend/reader.py b/pyscv/Frontend/reader.py
index 7694a94..a2a280b 100644
--- a/pysc-v/Frontend/reader.py
+++ b/pyscv/Frontend/reader.py
@@ -1,5 +1,5 @@
# TODO Logging is interesting for debugging purposes, decide what to do with it
-from logger import newlogger
+from .logger import newlogger
logger = newlogger(__name__)
#import logging
#logger.setLevel(logging.WARN)
diff --git a/pysc-v/InstructionSets/RV32C.py b/pyscv/InstructionSets/RV32C.py
index e740ac4..e740ac4 100644
--- a/pysc-v/InstructionSets/RV32C.py
+++ b/pyscv/InstructionSets/RV32C.py
diff --git a/pysc-v/InstructionSets/RV32D.py b/pyscv/InstructionSets/RV32D.py
index e69de29..e69de29 100644
--- a/pysc-v/InstructionSets/RV32D.py
+++ b/pyscv/InstructionSets/RV32D.py
diff --git a/pysc-v/InstructionSets/RV32F.py b/pyscv/InstructionSets/RV32F.py
index e69de29..e69de29 100644
--- a/pysc-v/InstructionSets/RV32F.py
+++ b/pyscv/InstructionSets/RV32F.py
diff --git a/pysc-v/InstructionSets/RV32I.py b/pyscv/InstructionSets/RV32I.py
index f2929f3..3fa02ad 100644
--- a/pysc-v/InstructionSets/RV32I.py
+++ b/pyscv/InstructionSets/RV32I.py
@@ -90,6 +90,9 @@ class B(Instruction):
self.opcode
)
+ def patch(imm):
+ self.imm = imm
+
class U(Instruction):
opcode = None
@@ -129,6 +132,8 @@ class J(Instruction):
self.opcode
)
+ def patch(imm):
+ self.imm = imm
diff --git a/pysc-v/InstructionSets/RV64I.py b/pyscv/InstructionSets/RV64I.py
index 72b8bcb..72b8bcb 100644
--- a/pysc-v/InstructionSets/RV64I.py
+++ b/pyscv/InstructionSets/RV64I.py
diff --git a/pysc-v/InstructionSets/__init__.py b/pyscv/InstructionSets/__init__.py
index e69de29..e69de29 100644
--- a/pysc-v/InstructionSets/__init__.py
+++ b/pyscv/InstructionSets/__init__.py
diff --git a/pysc-v/InstructionSets/instructions.py b/pyscv/InstructionSets/instructions.py
index 00a3146..00a3146 100644
--- a/pysc-v/InstructionSets/instructions.py
+++ b/pyscv/InstructionSets/instructions.py
diff --git a/pysc-v/main.py b/pyscv/main.py
index 2d6f6a5..8cdc08f 100644
--- a/pysc-v/main.py
+++ b/pyscv/main.py
@@ -2,4 +2,7 @@
# -> PC has to be a global variable, updated by each instruction to the next val
# So user can set the PC by hand and call next(run) and make the code jump!
-
+pc = 0
+while True:
+ inst = fetch_instruction(pc)
+ pc = inst.execute()
diff --git a/pysc-v/memory.py b/pyscv/memory.py
index 84bf0bd..84bf0bd 100644
--- a/pysc-v/memory.py
+++ b/pyscv/memory.py
diff --git a/pysc-v/registers/RV32F.py b/pyscv/registers/RV32F.py
index 8e3fd28..8e3fd28 100644
--- a/pysc-v/registers/RV32F.py
+++ b/pyscv/registers/RV32F.py
diff --git a/pysc-v/registers/RV32I.py b/pyscv/registers/RV32I.py
index a723064..a723064 100644
--- a/pysc-v/registers/RV32I.py
+++ b/pyscv/registers/RV32I.py
diff --git a/pysc-v/registers/__init__.py b/pyscv/registers/__init__.py
index e69de29..e69de29 100644
--- a/pysc-v/registers/__init__.py
+++ b/pyscv/registers/__init__.py