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authorEkaitz Zarraga <ekaitz@elenq.tech>2021-05-24 20:45:04 +0200
committerEkaitz Zarraga <ekaitz@elenq.tech>2021-05-24 20:45:04 +0200
commit309492a16167fc1cad65050ec5080c3a943bc629 (patch)
tree815a82be1b541f222a6e473f3ee0c06a512ad4a9
parent0869583f08a64fb0ec4c833466f261cacd060d3b (diff)
Add RV64I instruction support
-rw-r--r--pysc-v/InstructionSets/RV64I.py63
1 files changed, 63 insertions, 0 deletions
diff --git a/pysc-v/InstructionSets/RV64I.py b/pysc-v/InstructionSets/RV64I.py
new file mode 100644
index 0000000..72b8bcb
--- /dev/null
+++ b/pysc-v/InstructionSets/RV64I.py
@@ -0,0 +1,63 @@
+from .instructions import Instruction, InstructionSet
+from ctypes import c_uint32
+from .RV32I import *
+
+RV64I = InstructionSet()
+
+class ShiftImm64(ShiftImm):
+ # NOTE: This is an special type used for shifting operations because they
+ # have 7 bits left after the maximum shift (5bits -> 32 rotations)
+ # they can apply.
+ # In RV64I they can indicate rotation with 1 bit more (64 rotations) so
+ # they use a funct6 instead.
+ funct6 = None
+ funct3 = None
+ opcode = None
+
+ def __init__(self, rd, rs, imm):
+ self.rd = rd
+ self.rs = rs
+ self.imm = imm
+
+ def compile(self):
+ return c_uint32(
+ (self.funct6 << 26) +\
+ (self.imm << 20) +\
+ (self.rs << 15) +\
+ (self.funct3 << 12) +\
+ (self.rd << 7) +\
+ self.opcode
+ )
+
+@RV64I.instruction
+class slli(ShiftImm64):
+ name = "slli"
+ opcode = 0b0010011
+ funct3 = 0b001
+ funct6 = 0b000000
+
+@RV64I.instruction
+class srli(ShiftImm64):
+ name = "srli"
+ opcode = 0b0010011
+ funct3 = 0b101
+ funct6 = 0b000000
+
+@RV64I.instruction
+class srai(ShiftImm64):
+ name = "srai"
+ opcode = 0b0010011
+ funct3 = 0b101
+ funct6 = 0b010000
+
+@RV64I.instruction
+class sd(S):
+ name = "sd"
+ opcode = 0b0100011
+ funct3 = 0b011
+
+@RV64I.instruction
+class ld(I):
+ name = "ld"
+ opcode = 0b0000011
+ funct3 = 0b011