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author | Ekaitz Zarraga <ekaitz@elenq.tech> | 2021-04-25 00:08:27 +0200 |
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committer | Ekaitz Zarraga <ekaitz@elenq.tech> | 2021-04-25 00:08:27 +0200 |
commit | 6424e20409608dcc083f2dadaf381e101649313f (patch) | |
tree | 69bac9aade091549ae4437b721c45b96b5e387f6 | |
parent | 6e3e5e6aaf1bc9b8f2d787fdf5f9bbd714776b5d (diff) |
Work on J instruction, WIP
-rw-r--r-- | pysc-v/InstructionSets/RV32I.py | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/pysc-v/InstructionSets/RV32I.py b/pysc-v/InstructionSets/RV32I.py index 967b24d..dcdee36 100644 --- a/pysc-v/InstructionSets/RV32I.py +++ b/pysc-v/InstructionSets/RV32I.py @@ -50,7 +50,19 @@ class U(Instruction): pass class J(Instruction): - pass + # TODO check if it's correct + opcode = None + + def __init__(self, rd, imm): + self.rd = rd + self.imm = imm + + def compile(self): + return c_uint32( + (self.imm << 12) +\ + (self.rd << 7) +\ + self.opcode + ) class add(R): |