summaryrefslogtreecommitdiff
path: root/pyscv
diff options
context:
space:
mode:
authorEkaitz Zarraga <ekaitz@elenq.tech>2021-07-23 20:28:36 +0200
committerEkaitz Zarraga <ekaitz@elenq.tech>2021-07-23 20:28:36 +0200
commit309d36182ef32a1bc5bff84f39e9e81db0ddb9a6 (patch)
tree210ceb9300ed47f00356ff5e276c79d0b4deca40 /pyscv
parentd4426ef4435be0b033af16e60e74e73ce700a6a0 (diff)
Add baseassembler
Diffstat (limited to 'pyscv')
-rw-r--r--pyscv/baseassembler.py33
1 files changed, 33 insertions, 0 deletions
diff --git a/pyscv/baseassembler.py b/pyscv/baseassembler.py
new file mode 100644
index 0000000..e65a5bd
--- /dev/null
+++ b/pyscv/baseassembler.py
@@ -0,0 +1,33 @@
+from registers.RV32I import *
+from InstructionSets.RV64I import *
+
+
+Regs = RegistersRV32I()
+
+def x(registerName):
+ return Regs.getPos(registerName)
+
+def compileBigEndian(instruction):
+ hexrepr = hex(instruction.compile().value)
+ hexval = hexrepr[2:]
+ if len(hexval) < 8:
+ hexval = "0" * (8 - len(hexval)) + hexval
+
+ final = ""
+ for i in range(0,8,2):
+ final += hexval[i:i+2] + " "
+ return final.rstrip().upper()
+
+def compileLittleEndian(instruction):
+ hexrepr = hex(instruction.compile().value)
+ hexval = hexrepr[2:]
+ if len(hexval) < 8:
+ hexval = "0" * (8 - len(hexval)) + hexval
+
+ final = ""
+ for i in range(0,8,2):
+ final += hexval[i:i+2] + " "
+ final = final.rstrip().upper()
+ return " ".join(reversed(final.split(" ")))
+
+