6 files changed, 130 insertions, 0 deletions
diff --git a/pysc-v/InstructionSets/RV32C.py b/pysc-v/InstructionSets/RV32C.py
new file mode 100644
index 0000000..e740ac4
--- /dev/null
+++ b/pysc-v/InstructionSets/RV32C.py
@@ -0,0 +1,29 @@
+from instructions import Instruction, InstructionSet
+
+class Compressed(Instruction):
+    size = 2
+
+
+class CR(Compressed):
+    pass
+
+class CI(Compressed):
+    pass
+
+class CSS(Compressed):
+    pass
+
+class CIW(Compressed):
+    pass
+
+class CJ(Compressed):
+    pass
+
+class CB(Compressed):
+    pass
+
+class CL(Compressed):
+    pass
+
+class CS(Compressed):
+    pass
diff --git a/pysc-v/InstructionSets/RV32D.py b/pysc-v/InstructionSets/RV32D.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/pysc-v/InstructionSets/RV32D.py
diff --git a/pysc-v/InstructionSets/RV32F.py b/pysc-v/InstructionSets/RV32F.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/pysc-v/InstructionSets/RV32F.py
diff --git a/pysc-v/InstructionSets/RV32I.py b/pysc-v/InstructionSets/RV32I.py
new file mode 100644
index 0000000..967b24d
--- /dev/null
+++ b/pysc-v/InstructionSets/RV32I.py
@@ -0,0 +1,71 @@
+from instructions import Instruction, InstructionSet
+
+RV32I = InstructionSet()
+
+class R(Instruction):
+    funct3  = None
+    funct7  = None
+    opcode  = None
+    def __init__(self, rd, rs1, rs2):
+        self.rd  = rd
+        self.rs1 = rs1
+        self.rs2 = rs2
+
+    def compile(self):
+        # TODO: ensure sizes and convert register names to number...
+        return c_uint32(
+            (self.funct7  << 25) +\
+            (self.rs2     << 20) +\
+            (self.rs1     << 15) +\
+            (self.funct3  << 12) +\
+            (self.rd      <<  7) +\
+            self.opcode
+        )
+
+class I(Instruction):
+    funct3 = None
+    opcode = None
+
+    def __init__(self, rd, rs, imm):
+        self.rd = rd
+        self.rs = rs
+        self.imm = imm
+
+    def compile(self):
+        return c_uint32(
+            (self.imm    << 20) +\
+            (self.rs     << 15) +\
+            (self.funct3 << 12) +\
+            (self.rd     <<  7) +\
+            self.opcode
+        )
+
+class S(Instruction):
+    pass
+
+class B(Instruction):
+    pass
+
+class U(Instruction):
+    pass
+
+class J(Instruction):
+    pass
+
+
+class add(R):
+    name    = "add"
+    opcode  = 0b0110011
+    funct3  = 0b000
+    funct7  = 0b0000000
+
+    def execute(self):
+        return pc + self.size
+
+class addi(I):
+    name    = "addi"
+    opcode  = 0b0010011
+    funct3  = 0b000
+
+    def execute(self):
+        pass
diff --git a/pysc-v/InstructionSets/__init__.py b/pysc-v/InstructionSets/__init__.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/pysc-v/InstructionSets/__init__.py
diff --git a/pysc-v/InstructionSets/instructions.py b/pysc-v/InstructionSets/instructions.py
new file mode 100644
index 0000000..5587f2e
--- /dev/null
+++ b/pysc-v/InstructionSets/instructions.py
@@ -0,0 +1,30 @@
+from ctypes import c_uint32
+
+
+class Instruction:
+    size = 4  # Instruction size in bytes
+
+    def __init__(self):
+        pass
+
+    def compile(self):
+        # return the binstream of the instruction in a c_uint32
+        pass
+
+    def execute(self):
+        # executes the instruction and returns the next program counter
+        return
+
+class InstructionSet:
+    def __init__(self, init=None):
+        self.data = dict()
+
+    def add_instruction(self, ins):
+        if ins.name not in self.data:
+            self.data[ins.name] = ins
+
+
+if __name__ == "__main__":
+    # TODO This is the interface i'd love to have
+    addins = add("x5","x2","zero")
+    j("labelName")