bibliography: Add Heron

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diff --git a/bibliography.bib b/bibliography.bib
index 5dc9d5f..2a6527e 100644
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+++ b/bibliography.bib
@@ -382,6 +382,40 @@
   doi={10.1109/ISCA.2014.6853201}
 }
 
+@inproceedings{Heron:Ramsay,
+    author = {Ramsay, Craig and Stewart, Robert},
+    title = {Heron: Modern Hardware Graph Reduction},
+    year = {2024},
+    isbn = {9798400716317},
+    publisher = {Association for Computing Machinery},
+    address = {New York, NY, USA},
+    url = {https://doi.org/10.1145/3652561.3652564},
+    doi = {10.1145/3652561.3652564},
+    abstract = {FPGAs have enjoyed exponential growth of on-chip hardware
+        resources — reason to reinvestigate hardware implementations of
+        functional languages. This paper presents Heron, an FPGA-based
+        special purpose processor core for pure, non-strict functional
+        languages. We co-design its language semantics and parametrised
+        design, gaining a high reductions-per-cycle performance metric. The
+        Heron core is energy efficient, performing up to six times as many
+        reductions per cycle as GHC. Despite its infancy, a 193 MHz Heron
+        core outperforms wall-clock time for a mid-range Intel i3 1.9 GHz
+        mobile CPU for 5 of these benchmarks and is competitive with an
+        Alder Lake Intel i7 CPU. Its performance-per-Watt shows that the
+        Heron core is a compelling solution for embedded applications. The
+        simplicity of Heron’s design results in just 2\% FPGA resource
+        usage, paving the way for future single-chip parallelism, further
+        improving absolute performance.},
+    booktitle = {Proceedings of the 35th Symposium on Implementation and
+        Application of Functional Languages},
+    articleno = {3},
+    numpages = {12},
+    keywords = {FPGAs, functional languages, graph reduction, hardware
+        accelerators},
+    location = {Braga, Portugal},
+    series = {IFL '23}
+}
+
 
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