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author | Ekaitz Zarraga <ekaitz@elenq.tech> | 2021-01-23 21:12:29 +0100 |
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committer | Ekaitz Zarraga <ekaitz@elenq.tech> | 2021-01-23 21:12:29 +0100 |
commit | bf457baaf3dc5e05dd16eeca2650ebd15ee9a226 (patch) | |
tree | 684a26fcc71391ab79532f3205acaff013e6dd47 | |
parent | 1be1d9635f88274b751decd4b67d70105a402436 (diff) |
Add spike for RISC-V development
-rw-r--r-- | riscv.scm | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/riscv.scm b/riscv.scm new file mode 100644 index 0000000..176295a --- /dev/null +++ b/riscv.scm @@ -0,0 +1,29 @@ +(define-module (riscv) + #:use-module (guix packages) + #:use-module (guix git-download) + #:use-module ((guix licenses) #:prefix license:) + #:use-module (guix build-system gnu) + #:use-module (gnu packages bootloaders) ; For spike + ) + + +(define-public spike + (package + (name "spike") + (version "1.0.0") + (source (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/riscv/riscv-isa-sim.git") + (commit (string-append "v" version)))) + (file-name (git-file-name name version)) + (sha256 (base32 "1hcl01nj96s3rkz4mrq747s5lkw81lgdjdimb8b1b9h8qnida7ww")))) + + (propagated-inputs + `(("dtc" ,dtc))) + (build-system gnu-build-system) + (home-page "https://github.com/riscv/riscv-isa-sim") + (description "Spike, the RISC-V ISA Simulator, implements a functional +model of one or more RISC-V harts.") + (synopsis "RISC-V ISA Simulator") + (license license:gpl3+))) |